UBS Teardown of Huawei Atlas 950 Super Node: Bullish on SMIC, AMEC, Montage Tech and More
Nashnova编辑部
UBS deep-dives into Huawei's Ascend 950 chip and Atlas 950 SuperPod, arguing Huawei is using system-level engineering to offset weaker process nodes — and names six Chinese semiconductor firms as likely beneficiaries.
What makes the Ascend 950 competitive despite older process tech?
The Ascend 950 uses a less advanced manufacturing process, yet some specs already match Nvidia's H100. This means → Huawei is not competing on process leadership but on integrating compute, memory, and interconnect into a single optimized system.
The chip uses a dual-die chiplet design — two dies working together — built on Huawei's third-generation DaVinci architecture, supporting low-precision formats like FP8 and MXFP4. In plain terms = trade raw precision for speed, and let software recover the accuracy.
UBS expects other Chinese chipmakers to copy this "system over process" playbook. The competitive benchmark shifts from "who has the most advanced node" to "who delivers the highest effective throughput."
Why two SKUs instead of one universal chip?
The Ascend 950 ships in two variants: 950PR — 128 GB capacity, 1.6 TB/s bandwidth — optimized for prefill (processing a large input block in one pass) and recommendation workloads.
950DT — 144 GB capacity, 4 TB/s bandwidth — optimized for decode (generating output token by token) and training. More memory, higher bandwidth, heavier compute.
This means → Huawei splits optimization by workload type rather than building one do-everything chip. UBS sees this split as a template other Chinese vendors will have to adopt.
Why is the SuperPod's interconnect architecture the real differentiator?
The Atlas 950 SuperPod packs up to 1,024 Ascend 950 NPUs across 16 compute racks, linked by 800 Gbps LPO — linear pluggable optics, a high-speed optical interface. A full pod requires 4,096 LPO modules.
Each chip adds an I/O die on either side — 18 ports total — delivering up to 2 TB/s aggregate interconnect bandwidth. A dedicated CCU — collective communication unit — offloads coordination traffic between chips.
This reflects a broader shift: UBS argues the bottleneck is no longer how fast a single chip computes, but how fast a thousand chips move data between each other.
What is the new memory approach?
The Ascend 950 swaps externally sourced HBM2e for Huawei's in-house HiBL1.0 HBM — high-bandwidth memory. In plain terms = Huawei now builds the most critical memory module itself rather than relying on outside suppliers.
Memory follows a tiered design: on-chip buffer, L2 cache, and global memory in successive layers. This means → data is stored by access frequency, cutting transfer latency at each level.
Which six companies does UBS flag as beneficiaries?
Foundry and equipment: SMIC, NAURA, and AMEC — UBS calls all three critical to advanced-process breakthroughs.
Interconnect: Montage Technology — poised to gain from surging interconnect and memory-bandwidth demand. Advanced packaging: JCET — benefiting from rising 2.5D packaging (laying multiple chips side by side on one substrate) demand.
Test equipment: Changchuan Technology — benefiting from volume ramp of Chinese AI ASICs (chips custom-designed for specific AI tasks).
Can other Chinese firms replicate Huawei's playbook?
UBS observes that high-speed interconnect and memory bandwidth are growing in importance; "supernode" innovation is becoming the primary solution — consistent with what UBS saw at the World Artificial Intelligence Conference (WAIC).
Tighter collaboration between chip designers and customers — pushing operator-level optimization into the architecture-definition stage — is one of the most important levers for Chinese vendors to offset process constraints.
Whether other Chinese firms can effectively replicate Huawei's path will be the key verification point for tracking how China's AI-chip supply chain evolves competitively.
Content is for reference only, not financial advice.