ZEISS: EUV Gap Constrains China's Chip Catch-Up
Miles Bennett
Two senior Zeiss executives say China's attempts to bypass EUV lithography through advanced packaging and multi-patterning face fundamental limits — the process gap cannot be closed by workarounds alone.
How far behind is China's process technology?
Zeiss SMT CEO Frank Rohmund says the industry consensus places China's leading edge at roughly 7 nm.
The global frontier has moved from 3 nm toward 2 nm, with preparation underway for the next-generation A14 node.
This means → China trails the cutting edge by at least two to three full generations, and the gap is still widening.
Can multi-patterning substitute for EUV?
In theory, multi-patterning — exposing the same wafer multiple times to print finer features — can approach 5 nm-class results.
The trade-off: costs rise sharply, yields drop, and commercial competitiveness suffers.
In plain terms = whether you *can* make the chip is one question; whether you can *sell it competitively* is another — multi-patterned chips are too expensive with too many defects.
Rohmund adds: with massive, sustained government subsidies some paths may remain viable, but this model cannot compete with the mainstream long-term.
Can advanced packaging replace EUV?
Zeiss CTO Thomas Stammler is explicit: advanced packaging — assembling multiple chiplets into one package — and process shrinkage are complementary, not interchangeable.
Using a mature node and adding transistors through packaging integration can boost system performance — but larger transistors mean more silicon consumed, higher power draw, and rising packaging costs.
This means → packaging can close part of the gap, but not the fundamental part — the per-transistor efficiency deficit is beyond packaging's reach.
Where does Zeiss itself stand?
Rohmund confirms that neither Zeiss nor ASML can export EUV-related technology or equipment to China; the company strictly complies with export controls.
This reflects a broader reality: the EUV supply-chain blockade extends well beyond ASML — Zeiss, as the core supplier of EUV optical systems, is equally covered.
What is the real trump card in future chip competition?
Stammler's assessment: future AI-chip performance gains will depend on both process shrinkage and system-level innovation — neither leg alone is enough.
Yet these new techniques cannot fully replace the advantages of EUV or next-generation High-NA EUV — an even higher-precision form of extreme-ultraviolet lithography.
In plain terms = in the AI era, semiconductor competition still comes down to who has the more advanced lithography — EUV and High-NA EUV are the entry ticket to that race.
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