AMD CEO Lisa Su Visits Taiwan to Compete for AI Chip Production Capacity
nashnova research
AMD CEO Lisa Su landed in Taiwan for the second time in five months, holding closed-door meetings with TSMC and packaging, testing, and substrate suppliers — the bottleneck in AI chips is no longer fabrication alone but who can secure every link in the supply chain.
Why did Lisa Su visit Taiwan twice in five months?
Su arrived on October 5, less than five months after her May trip. No public events were scheduled — every meeting was behind closed doors.
She met with TSMC, packaging houses, test firms, and substrate makers. This means → AMD is not locking down one step — it needs the entire chain from wafer to assembly.
In plain terms = the AI chip problem today is not "can you design it?" but "can you get every supplier lined up?" — and that takes the CEO showing up in person.
How far has the capacity war spread?
Supply-chain sources say Nvidia, Intel, and other major customers have been raising prices and prepaying deposits to grab packaging, testing, and substrate slots.
The bottleneck has spread from 2 nm and 3 nm fabrication into CoWoS advanced packaging, testing, and substrates.
This reflects a shift in AI chip competition: the fight is no longer about who has the best silicon — it is about who can get chips made, packaged, tested, and mounted on a server.
What is AMD's two-track packaging strategy?
Track one: keep pushing for more CoWoS — a technique that places multiple chips side by side in one package — and SoIC-X advanced packaging capacity from TSMC.
Track two: roll out EFB (Elevated Fanout Bridge), a 2.5D bridge-interconnect approach built with ASE (日月光), SPIL (矽品), and validated at panel level with Powertech (力成) — independent of TSMC's packaging lines.
This means → AMD does not want all its eggs in the TSMC basket. If Nvidia fills CoWoS capacity, EFB gives AMD a backup lane.
Where does the substrate and supply-chain buildout stand?
On the substrate side, Unimicron (欣興), Nan Ya PCB (南亞電路板), and Kinsus (景碩) have all joined AMD's Taiwan supply chain.
In May, AMD announced over $10 billion in investment in Taiwan's industrial ecosystem and disclosed that its next-gen EPYC processor, Venice, has entered production on TSMC's 2 nm process.
In plain terms = AMD is putting serious money down and locking in partners to make sure no single step — from chip to server — becomes the weak link.
What does this flash visit need to accomplish?
AMD must secure upstream and downstream capacity simultaneously to keep next-gen EPYC processors, AI accelerators, and the Helios rack platform on schedule.
Whether Su can lock in capacity amid tightening packaging and substrate supply is the key variable for AMD's AI product line hitting its volume targets.
This reflects a broader reality: in the AI hardware arms race, the CEO personally managing the supply chain is no longer a signal of "taking it seriously" — it is a baseline competitive move.
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