China's 3D DRAM Moves from Lab to Fab, but Mass Production Still Faces Equipment Bottlenecks
nashnova research
Chinese institutions are pushing 3D DRAM from academic papers toward wafer-level validation, aiming to bypass EUV lithography restrictions through vertical stacking — but the etch and deposition tools needed for mass production remain publicly unverified, and China's timeline still trails the global 2030 target.
Why is China betting on 3D DRAM?
Samsung and SK hynix plan to introduce high-NA EUV lithography into DRAM lines around 2028. Chinese chipmakers cannot obtain EUV equipment at all, and U.S. export controls block tools needed for DRAM at 18 nm half-pitch and below.
3D DRAM — stacking memory cells vertically instead of shrinking them on a flat plane — shifts the density challenge from lithography to deposition and etching. This means → even without cutting-edge lithography, capacity can theoretically keep growing if the etch and deposition tools are good enough.
In plain terms = others gain density by "etching finer"; China is forced to try "stacking higher."
Where does CXMT stand today?
CXMT (长鑫存储) is now the world's fourth-largest DRAM maker. Counterpoint Research data show its global DRAM revenue share hit 10% in Q2 2026, up from 4% a year earlier and 8% the prior quarter.
Samsung held 39%, SK hynix 26%, Micron 25% — the top three still control roughly nine-tenths of the market. CXMT is the only challenger with a visibly rising share curve.
This reflects real capacity expansion on mature-process DRAM, but 3D DRAM is a next-generation technology still in R&D validation — a separate matter from today's revenue gains.
What are the two technical paths?
Path one: 1T1C + IGZO — CXMT and the Beijing Superstring Academy of Memory Technology (SAMT) use IGZO — indium gallium zinc oxide, a semiconductor with extremely low leakage — as the access transistor, stacking layers laterally. They have completed 12-inch wafer validation, published at IEDM 2025.
Path two: 2T0C — led by IMECAS (中科院微电子所) and SAMT, this design replaces the traditional capacitor with two transistors, eliminating the capacitor entirely. A four-layer stacked 3D 2T0C DRAM was presented at VLSI 2026 in June.
IGZO is critical to both paths: its ultra-low leakage lets cells retain data far longer than silicon transistors, and it can be processed at low temperatures — allowing more memory layers to be added on top of existing circuitry. In plain terms = IGZO both "remembers well" and "tolerates low heat," making it the foundation for vertical stacking.
Where is the equipment bottleneck?
As layers increase, controlling etch depth, sidewall profile, film uniformity, and inter-layer alignment grows exponentially harder — every one of these steps depends on equipment capability.
NAURA (北方华创) has drawn market attention for 3D DRAM etch-related progress and reportedly published research in an IEEE journal covering 3D DRAM fabrication including etch processes. But actual process conditions, customer qualification, and production readiness remain very limited in the public record.
This means → the gap between "publishing a paper" and "qualifying on a production line" has not been publicly bridged. Whether NAURA can form a working fab partnership is the pivotal variable for mass production.
Where are global peers?
Samsung disclosed a 16-layer 3D DRAM plan at IMW 2024. Its vertical-channel-transistor (VCT) DRAM is positioned as a transitional architecture; a Samsung VP said commercial 3D DRAM is expected around 2030.
SK hynix's roadmap likewise places 3D DRAM mass production around 2030. In August 2025, Belgium's imec and Ghent University also reported related materials research.
In plain terms = every major player sees 3D DRAM as four to five years away from production. China's R&D pace is not ahead. The key question is whether breakthroughs in domestic deposition and etch equipment can close — or even beat — that timeline.
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