Global Foundry 2.0 Revenue Hits Record in Q2, TSMC Accounts for 42%
nashnova research
Global Foundry 2.0 revenue reached a record $96.6 billion in Q2 2026, up 25% year-on-year; TSMC alone took 42%, but non-TSMC foundries are accelerating fast, and packaging capacity is emerging as the supply chain's next hard constraint.
What is Foundry 2.0, and why use this framework?
Foundry 2.0 is a Counterpoint Research metric that bundles traditional foundries, non-memory IDMs — companies that design and fabricate their own chips — OSAT firms, and photomask suppliers into one revenue figure.
This means → it is far broader than the traditional "TSMC + UMC + SMIC" view, capturing the full cost chain from chip design through packaging and test.
Under this framework, Q2 total revenue hit $96.6 billion, up 25% YoY and 11% QoQ — an all-time high.
Why is TSMC still the biggest winner?
TSMC posted Q2 revenue of $40.2 billion, up 34% YoY, claiming roughly 42% of the Foundry 2.0 market.
Growth rests on three pillars: strong advanced-node demand, wafer price increases, and CoWoS advanced-packaging expansion.
The report projects TSMC's full-year 2026 revenue growth at about 43%. This means → TSMC is gaining share, raising prices, and expanding capacity simultaneously — all three amplifying each other.
Which non-TSMC foundries are accelerating?
Non-TSMC pure-play foundry revenue grew 18% YoY, nearly doubling the 9% pace in Q1.
Leaders: SMIC (中芯国际) +36%, Nexchip +21%, Hua Hong +17%, Vanguard +20%, UMC +9%.
In plain terms = this wave is driven by AI-infrastructure demand for power-management ICs and interposers, not a consumer rebound — consumer demand remains soft.
Where do SMIC and Samsung each stand?
SMIC's utilization rate hit 93.7%; wafer shipments rose 14% QoQ and average selling prices climbed 5.7% QoQ. Management attributed the growth to Chinese customers' demand for AI-related chips (excluding CPUs/GPUs) and said it will accelerate new-line ramp-ups.
Samsung raised prices on select new orders in July — up to 15% on its 4 nm SF4 and 5 nm SF5 nodes, and nearly 10% on 8 nm wafers. Its Pyeongtaek SF4 line is running at full capacity. Yet Samsung holds only about 4% of the Foundry 2.0 market.
This reflects a shared push to raise prices and expand, but the report adds a key qualifier: neither Samsung nor Intel currently matches TSMC in advanced-node scale, yield, or packaging execution.
Why is packaging becoming the next bottleneck?
OSAT revenue rose 22% YoY to $12.6 billion; ASE grew 24%, Amkor 26%.
TSMC's CoWoS — a technology that packages multiple chips together at wafer level — faces a supply–demand gap of roughly 20% in 2026. As in-house capacity scales to 185,000 wafers per month, the gap is expected to narrow to about 10% by 2027.
Amkor announced a Phase 2 expansion of its Arizona advanced-packaging campus, adding 60,000 m² of cleanroom space for a planned total investment of about $12 billion, with completion targeted for late 2029.
Can growth hold in H2, and where is the constraint?
The report projects Foundry 2.0 revenue will sustain double-digit YoY growth through H2 2026.
This means → the ceiling is not on the demand side but on the supply side — advanced packaging, substrates, and test capacity are the binding constraints for data-center chip deployment.
In plain terms = the chips can be fabricated, but if packaging and testing cannot keep pace, the entire chain's growth expectations will not be met.
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