HBM Capacity Shift Drives DDR4 Contract Price Gains to Outpace DDR5
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Samsung, SK Hynix and Micron are funneling wafer capacity toward HBM and DDR5, squeezing DDR4 supply — over the past three months DDR4 contract prices rose 24%, outpacing DDR5's 20%, an unusual reversal in which the older standard is climbing faster than its successor.
Why is the older memory rising faster?
All three major memory makers are tilting wafer capacity toward HBM and DDR5, sharply cutting DDR4 production lines.
Per a Barclays report, DDR4 contract prices rose 24% over the past three months versus 20% for DDR5; in October alone, DDR4 gained 4% month-on-month, DDR5 3%.
This means → DDR4 is not rallying on demand — it is rallying because no one wants to allocate capacity to it anymore. Supply-side contraction is driving the price.
Why are long-term supply agreements loosening too?
Traditional long-term agreements (LTAs — contracts that lock in prices and volumes ahead of time) include price floors and ceilings to smooth volatility, but that mechanism is breaking down under supply-demand imbalance.
UBS notes that Samsung and SK Hynix typically lock pricing on roughly 60% to 70% of contracted volume in five-year deals, with the rest floating at market rates.
This means → LTA pricing is shifting from "locked protection" to "tracking spot" — the very tool buyers used to hedge risk is now amplifying their exposure to price swings.
Are downstream buyers already cutting specs?
Tesla CEO Elon Musk reportedly considered reducing the memory capacity of the next-generation AI5 chip in response to procurement difficulties and rising prices.
Barclays characterized such adjustments as temporary measures to cope with supply shortages, warning that medium- to long-term risks remain.
In plain terms = it is not that they want less memory — they cannot get it or afford it, so they are dialing specs down as a stopgap.
When does the shortage actually peak?
Citi expects the DRAM supply gap to peak at 13.9% in Q4 2027, with the NAND Flash gap reaching 8.3% in Q1 2028 — shortages lasting at least through 2028.
Sigmaintell, a market research firm, sees it very differently: the DRAM gap narrows from 5.7% in 2026 to just 0.7% in 2027, NAND Flash from 4.5% to 1%, with the overall shortage peaking in 2026.
This means → the two forecasts diverge by nearly two years on when the shortage peaks — the valuation recovery timeline for memory stocks is deeply uncertain, and this disagreement itself is the core variable the market is watching.
Does the memory shortage peak in 2026 — or last through 2028?
BULL
Gap closing fast
Sigmaintell sees DRAM gap at just 0.7% in 2027; shortage peaks next year.
Capacity ramp under way
HBM wafer capacity grows over 70% in 2026, another 50%-55% in 2027.
BEAR
Demand outstrips capacity
Citi projects a 13.9% DRAM gap in Q4 2027; shortage persists through 2028.
GPU demand compounds
If 2027 GPU + ASIC demand nears 200 million units all using 12-layer HBM, the gap could hit 30%.
In plain terms = the two sides are using different data sources and demand assumptions. Citi bets AI demand keeps surging beyond what capacity can serve; Sigmaintell believes expansion will catch up. The investor's job is not to decide who is right, but which demand scenario they are betting on.
Why would HBM drop from 12 layers back to 8?
Major GPU and custom-ASIC makers are considering 8-layer HBM in next-generation designs instead of 12-layer, with roughly 40% of 2027 HBM shipments expected to use the 8-layer spec.
8-layer stacks offer higher yields and shorter lead times — this reflects a priority shift: "can we get supply at all" matters more right now than "can we get the top spec."
HBM4 pricing in 2027 could reach $1,400–$1,600 per unit, roughly 1.8× the 2026 level; switching to 8-layer brings the unit price down, but the per-bit cost actually rises.
Fewer layers does not mean lower cost?
Both HBM4 and HBM4E designs rely on a custom logic base die — the controller chip at the very bottom of the stack — whose cost does not fall when fewer memory layers are stacked on top.
In plain terms = cutting layers saves on the memory dies above, but the base stays the same price — total cost barely drops, and spread across fewer bits it is actually more expensive per bit.
This means → the real driver behind the shift to lower-spec HBM is a capacity bottleneck, not cost reduction — once supply-chain constraints ease, layer counts are expected to climb back up.
市场有风险，内容仅供研究参考，不构成投资建议。