Micron Partners with TSMC to Advance Custom HBM; NVHBM Delivers 30% Bandwidth Improvement
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Micron is co-developing NVHBM with NVIDIA, moving the memory controller into the HBM base die for up to 30% more bandwidth and 15% lower power. The base die will be fabbed by TSMC — a shift from in-house to outsourced logic, trading process capability for deeper customization.
What exactly does NVHBM change?
The key move: the memory controller, previously on the compute die, is relocated into the HBM base die — the logic chip at the bottom of the memory stack that directs the storage layers above it.
This means → memory manages its own data movement, freeing area and power budget on the compute die so more silicon goes to computation.
Micron's stated potential upside: up to 30% higher bandwidth per stack, up to 15% lower HBM power, and up to 67% smaller PHY and support-circuit footprint. Micron stresses these are potential technical gains; actual performance depends on specific product and system designs.
Why hand the base die to TSMC?
During the HBM4 era Micron made its own base die. For NVHBM and the HBM4E standard line, TSMC takes over. Market estimates put the process node at possibly 3 nm, though Micron has not confirmed the exact node.
In plain terms = once the memory controller moves in, the base die's logic complexity jumps sharply — it needs a leading-edge process node to support it, and that is TSMC's strength, not a memory maker's.
This reflects a broader shift: HBM is evolving from a standard storage product into a semi-custom logic-plus-memory hybrid, blurring the line between memory companies and foundries.
How much pricing premium can customization deliver?
Micron president Manish Bhatia said HBM is already a premium product; adding customization should create higher value still.
NVHBM will also extend to the NVLink Fusion partner ecosystem — NVIDIA's framework for third-party chipmakers to co-design custom AI accelerators — broadening its addressable market.
Micron disclosed neither a specific price expectation nor a margin uplift target for NVHBM. Whether custom HBM actually delivers premium margins is the single most important proof point for this strategic pivot.
Where is capacity being built?
U.S.: two advanced DRAM fabs under way in Boise, Idaho; up to four large-scale fabs planned in New York State.
Asia: a new Hiroshima fab broke ground in July 2026; Singapore is adding a next-generation HBM advanced-packaging facility and expanding NAND capacity; Gujarat, India is building the country's first semiconductor assembly-and-test site.
Taiwan: Micron's Taiwan head Lu Tung-hui said capital spending over the coming years will rank among the world's largest, and called on Taiwanese equipment and materials suppliers to expand alongside Micron globally.
Why are customers willing to sign three-to-five-year deals?
Micron has signed three-to-five-year strategic agreements with major cloud and AI-chip customers; some contracts extend visibility to 2031. 2027 HBM bit supply is substantially locked in.
This means → customers are locking capacity with long-term commitments, signaling they view AI demand for high-bandwidth memory as structurally long-term, not a short-lived cycle.
For Micron, these contracts provide revenue certainty and underpin the capital-expenditure confidence needed to expand across multiple geographies simultaneously.
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