Samsung Sub-10nm DRAM Roadmap Shifts Toward Hybrid Bonding Technology
nashnova research
Samsung Electronics has made wafer-to-wafer hybrid bonding the baseline architecture for its first sub-10nm DRAM node (D0a), splitting vertical-channel transistor development into a separate branch. This means Samsung is betting its most advanced DRAM line on a packaging technique closer to proven manufacturing, while keeping the higher-risk architecture on a parallel track.
What exactly did Samsung change?
Per Digitimes, Samsung redesignated its D0a process baseline from a unified push to one led by wafer-to-wafer hybrid bonding — a packaging method that bonds two wafers face-to-face to form direct electrical connections.
The vertical-channel transistor (VCT) design — an approach that stands transistors upright to shrink cell area — has been moved to a standalone D0a-V branch.
In plain terms = the two technology tracks used to advance together; now Samsung has split them — hybrid bonding is the mainline, VCT is the experimental alternative.
Why pick hybrid bonding as the mainline?
Hybrid bonding is already proven in advanced packaging; TSMC and others use it in volume production of 3D-stacked chips.
This means → Samsung chose a path with higher process maturity as its baseline, reducing the technical uncertainty around D0a mass production.
VCT, while theoretically capable of a major reduction in DRAM cell area, represents a fundamental architectural shift — harder to manufacture and on a longer timeline.
Can this roadmap actually deliver?
The report comes from Digitimes' paywalled content; Samsung has not publicly confirmed the roadmap revision.
This reflects the fact that the information is still at the supply-chain intelligence stage, not yet an officially announced strategy.
The key validation point: whether hybrid bonding can achieve production-grade yields at the D0a node — if yields fall short, the strategic value of this mainline bet is diminished.
市场有风险，内容仅供研究参考，不构成投资建议。