SK Hynix HBM5 Completes TSMC Packaging Validation; HBM4 Enters NVIDIA's Vera Rubin Platform
nashnova research
SK Hynix has completed joint packaging validation of HBM5 with TSMC's CoWoS process, pushing next-next-gen memory development in lockstep with the foundry — while HBM4 has just been integrated into Nvidia's latest superchip, Vera Rubin, signaling an accelerating AI memory arms race.
How far along is HBM5 validation?
SK Hynix announced on September 28 that HBM5 has completed joint validation with TSMC's CoWoS packaging.
This means → next-next-generation HBM development is already running in parallel with the foundry, not waiting until the chip is finished to hand it off.
At TSMC's OIP Conference in Santa Clara on September 23, SK Hynix was named 3DFabric-HBM Integration Partner of the Year — the second consecutive year it has won the award.
SK Hynix has not yet disclosed HBM5's mass-production timeline, performance specs, or target customers.
Why does packaging need to come in this early?
HBM — high-bandwidth memory — works by stacking multiple DRAM dies vertically and placing them next to a GPU on the same substrate for high-speed data access.
As stack height and speed increase, memory performance depends heavily on how it is packaged with the processor. Designing the chip first and handing it to packaging later no longer works.
In plain terms = it used to be "build the chip, then box it." Now the box and the chip must be co-designed from day one. SK Hynix's packaging engineers have been collaborating with TSMC since early validation.
This reflects a shift in the AI-chip bottleneck — from "whose chip is faster" to "whose chip-to-package integration is tighter."
Where do HBM4 and the Vera Rubin platform stand?
At the OIP Conference, SK Hynix showcased a Vera Rubin platform configuration with 12-layer, 36 GB HBM4.
Also on display: 96 GB SOCAMM2 — a low-power DRAM module designed for CPU main memory.
This means → HBM4 has moved from the lab into platform integration, edging closer to volume production.
How much more AI storage demand is coming — and how will SSDs keep up?
SK Hynix engineer Daesik Park projected that the enterprise PCIe SSD market will grow from 509 EB in 2026 to 1,933 EB by 2030 — roughly a 3.8× increase.
To meet that demand, SK Hynix plans to split its PCIe 6 and PCIe 7 SSD controllers into smaller chiplets linked via the UCIe standard — a chip-to-chip interconnect protocol — replacing the traditional monolithic controller design.
In plain terms = instead of one big brain chip running everything inside the SSD, the job gets divided among smaller specialized blocks. Each block can be upgraded independently, shortening development cycles and adding flexibility.
What should we watch next?
Whether HBM5 stays on track for mass production is the key test of SK Hynix's technology lead.
Whether SK Hynix's deep packaging collaboration with TSMC can translate into a sustained edge over Samsung and other rivals remains an open question.
Park did not disclose the source behind his SSD demand forecast; the reliability of the figure awaits independent verification.
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