CXMT Plans to Invest 34 Billion Yuan to Expand R&D and Testing Capacity
nashnova research
CXMT's board approved ¥34.9 billion (~$5.2 billion) in twin investments covering R&D equipment and a captive test facility, less than three months after its IPO — a signal that the company is converting its over-raised capital into capacity at full speed.
Where does the ¥34.9 billion go?
Two projects: ¥24.1 billion for technology R&D, ¥10.8 billion for a Phase II back-end test base. Both require shareholder approval.
The R&D project sits at CXMT's Hefei 12-inch wafer fab and spans roughly two and a half years. Equipment purchases account for 93% (~¥22.4 billion). This means → almost all the money buys machines, not buildings; the goal is to advance the next generation of DRAM process technology.
The test base, operated by a wholly owned subsidiary, will build DRAM chip testing and module packaging facilities over about three years. Equipment and installation costs run to roughly ¥8.18 billion.
Where does the money come from — can the IPO proceeds support this?
CXMT's IPO raised a net ¥66.31 billion, overshooting its original target by about ¥36.8 billion. The company now plans to draw ¥18 billion from the excess (¥13 billion for R&D, ¥5 billion for testing) — nearly half the over-raised pool.
In plain terms = less than three months after listing, close to half of the surplus IPO cash already has a destination. The pace is aggressive.
The remaining funding gap relies on operating cash flow and other channels. First-half operating cash flow reached ¥131.16 billion — roughly 31 times the year-earlier figure — underpinned by the DRAM up-cycle's profit surge.
How far along are the existing projects?
The Hefei Phase I, Hefei Phase II, and Beijing production lines are all 96%–98% complete.
Contracted capital commitments stood at ¥52.44 billion at end-June, up 206.2% from ¥17.13 billion at end-2025 — a threefold jump.
Equipment and engineering prepayments rose 234.4% from end-2025 to roughly ¥4 billion. This means → a large volume of equipment orders has been placed but not yet delivered; capital spending will keep flowing in coming quarters.
Why build captive test capacity?
CXMT's stated rationale: as product lines and shipment volumes expand, external OSAT capacity may not keep pace.
The benefits are threefold: control over test scheduling + lower cost + stronger supply-chain security.
This reflects a broader push among Chinese DRAM makers toward vertical integration of fabrication and testing, especially as access to outside packaging and testing resources tightens.
The backdrop: HBM squeezes wafer capacity, tightening mainstream DRAM supply
Samsung Electronics executive Kim Taewoo said on September 29 that HBM is expected to consume nearly 30% of DRAM makers' total wafer capacity by 2027, up from roughly 20% today.
HBM — high-bandwidth memory, the high-speed memory paired with AI chips — shares the same wafer production lines as standard DRAM. This means → every incremental wafer HBM takes is one fewer wafer available for mainstream DRAM, creating a structural supply squeeze.
CXMT focuses on mainstream DRAM. First-half revenue mix: LPDDR 52.0%, DDR 46.2%. Long-term supply agreements with key customers are being negotiated in parallel.
G5 platform in mass production — how big is the yield gain?
CXMT's fifth-generation DRAM platform, G5, entered mass production in September. Two 24Gb LPDDR5X products are ramping simultaneously.
The key metric: normalized to 8Gb density, G5 delivers at least 50% more known-good die per wafer than the fourth generation.
In plain terms = from the same wafer, the new process cuts at least half again as many usable chips — directly lowering unit cost and raising fab utilization. This is the single most watched indicator for assessing CXMT's competitiveness.
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